Есть матрица LTN154X3-L03 от Samsung NP-R55. Интерфейс матрицы LVDS - 30pin 1ch 6bit.
Оказалось что в "стандартном" шнурке pinout отличается от "родного" для матрицы.

Реальных линий-сигналов от платы ноута на плату матрицы - 15шт.

распиновка:

1. VSS Ground  =>black    
2. VDD Power Supply +3.3V =>red
3. VDD Power Supply +3.3V =>red
4. VEEDID DCC 3.3V Power =>red
5.  -
6. CLKEDID DDC Clock =>blue
7. DATAEDID DDC data =>blue
8. RxIN0- LVDS Differencial Data Input (R0-R5,G0) =>blue
9. RxIN0+ LVDS Differencial Data Input (R0-R5,G0) =>blue
10. -
11. RxIN1-  LVDS Differencial Data Input (G0-G5,B0-B1) =>blue
12. RxIN1+ LVDS Differencial Data Input (G0-G5,B0-B1) =>blue
13. -
14. RxIN2- LVDS Differencial Data Input (B1-B5,Sync,DE) =>blue
15. RxIN2+ LVDS Differencial Data Input (B1-B5,Sync,DE) =>blue
16. -
17. RxCLK- LVDS Differencial Data Input (Clock) =>blue
18. RxCLK+ LVDS Differencial Data Input (Clock) =>blue
19. VSS Ground =>black

А вот в универсальном скалере "GOLD-A7" MT6820-B, который у меня в наличии:
1 LCD_PWR
2 LCD_PWR
3 LCD_PWR
4 GND
5 GND
6 GND
7 ATX0- LVDS 0DD 0- Signal
8 ATX0+ LVDS 0DD 0+ Signal
9 ATX1- LVDS 0DD 1- Signal
10 ATX1+ LVDS 0DD 1+ Signal
11 ATX2- LVDS 0DD 2- Signal
12 ATX2+ LVDS 0DD 2-+ Signal
13 GND
14 GND
15 ATCK- LVDS 0DD Clock- Signal
16 ATCK+ LVDS 0DD Clock+ Signal
17 ATX3- LVDS 0DD 3- Signal
18 ATX3+ LVDS 0DD 3+ Signal
19 BTX0- LVDS EVEN 0- Signal
20 BTX0+ LVDS EVEN 0+ Signal
21 BTX1- LVDS EVEN 1- Signal
22 BTX1+ LVDS EVEN 1+ Signal
23 BTX2- LVDS EVEN 2- Signal
24 BTX2+ LVDS EVEN 2+ Signal
25 GND
26 GND
27 BTCK- LVDS EVEN Clock- Signal
28 BTCK+ LVDS EVEN Clock+ Signal
29 BTX3- LVDS EVEN 3- Signal
30 BTX3+ LVDS EVEN 3+ Signal

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китайская версия, в принципе "1 в 1":

30Pin (разъем для ЖК LVDS интерфейс):

2x15pin (черный разъем) плата управления:

насколько я понимаю двухканальный стандарт 6 bit 2 ch 30pin

 30Pin (Разъем подключения к матрице):

PIN #	SIGNAL NAME	DESCRIPTION
1	GND	Ground
2	VCC	Power Supply
3	VCC	Power Supply
4	VEDID	DDC Power
5	NC	No Connection
6	CLKEDID	DDC Clock
7	DATAEDID	DDC data
8	Odd_RxIN0-	-LVDS differential data input
9	Odd_RxIN0+	+LVDS differential data input
10	GND	Ground
11	Odd_RxIN1-	-LVDS differential data input
12	Odd_RxIN1+	+LVDS differential data input
13	GND	Ground
14	Odd_RxIN2-	-LVDS differential data input
15	Odd_RxIN2+	+LVDS differential data input
16	GND	Ground
17	Odd_RxCLKIN-	-LVDS differential clock input
18	Odd_RxCLKIN+	+LVDS differential clock input
19	GND	Ground
20	Even_RxIN0-	-LVDS differential data input
21	Even_RxIN0+	+LVDS differential data input
22	GND	Ground
23	Even_RxIN1-	-LVDS differential data input
24	Even_RxIN1+	+LVDS differential data input
25	GND	Ground
26	Even_RxIN2-	-LVDS differential data input
27	Even_RxIN2+	+LVDS differential data input
28	GND	Ground
29	Even_RxCLKIN-	-LVDS differential clock input
30	Even_RxCLKIN+	+LVDS differential clock input